A hardware/application overlay model for large-scale neuromorphic simulation

Neuromorphic computing is gaining momentum as an alternative hardware platform for large-scale neural simulation. However, with several major devices and systems available and planned, often with very different characteristics, it is not always clear which platform is suitable for which application. Simulating the platform on conventional computers is typically too slow to be of use, but an alternative approach is to implement an ‘emulation’ of the hardware in FPGAs which can execute at near-hardware speeds but does not commit to a specific hardware architecture. We present an overlay model - a method which superimposes bespoke features on top of a standard template - in both hardware and software to implement neuromorphic architectures using the POETS (Partially Ordered Event Triggered Systems) system. This combination of overlays permits very large-scale simulations to be performed in real time for hardware exploration or application verification, while retaining the flexibility to redefine either the hardware or software layer, if results indicate potential to improve performance, or significant design problems. Using this system we simulate up to 500,000 neurons on a single-box system, that can be scaled to ∼4,000,000 neurons in an 8-box configuration. Results indicate the crucial constraint for real-time simulation: peak input spike rate per neuron; and help to optimise both hardware and software around neural application requirements. The preliminary architecture demonstrates the feasibility of an overlay model, while indicating directions for future neuromorphic systems. With POETS, we introduce a platform that can help to shape and investigate the neuromorphic architectures of the future

Hypocalcemia in hospitalized patients with COVID‑19: roles of hypovitaminosis D and functional hypoparathyroidism

Introduction Despite the high prevalence of hypocalcemia in patients with COVID-19, very limited studies have been designed to evaluate etiologies of this disorder. This study was designed to evaluate the status of serum parameters involved in calcium metabolism in patients with COVID-19 and hypocalcemia. Materials and methods This cross-sectional study was conducted on 123 hospitalized patients with COVID-19. Serum concentrations of PTH, 25 (OH) D, magnesium, phosphate, and albumin were assessed and compared across three groups of moderate/severe hypocalcemia (serum total calcium<8 mg/dl), mild hypocalcemia (8 mg/dl≤serum total calcium<8.5 mg/ dl) and normocalcemia (serum total calcium≥8.5 mg/dl). Multivariate analyses were performed to evaluate the independent roles of serum parameters in hypocalcemia. Results In total, 65.9% of the patients had hypocalcemia. Vitamin D defciency was found in 44.4% and 37.7% of moderate/ severe and mild hypocalcemia cases, respectively, compared to 7.1% in the normal serum total calcium group (P=0.003). In multivariate analysis, vitamin D defciency was independently associated with 6.2 times higher risk of hypocalcemia (P=0.001). Only a minority of patients with hypocalcemia had appropriately high PTH (15.1% and 14.3% in mild and moderate/severe hypocalcemia, respectively). Serum PTH was low/low-normal in 40.0% of patients with moderate/severe low-corrected calcium group. Magnesium defciency was not associated with hypocalcemia in univariate and multivariate analysis. Conclusion Vitamin D defciency plays a major role in hypocalcemia among hospitalized patients with COVID-19. Inappropriately low/low-normal serum PTH may be a contributing factor in this disorder

Calcul non conventionnel avec des nanocomposants memristifs : du calcul numérique auxaccélérateurs neuromorphiques

By 2020, there will be 50 to 100 billion devices connected to the Internet. Two domains of hot researchto address these high demands of data processing are the Internet of Things (IoT) and Big Data. Thedemands of these new applications are increasing faster than the development of new hardwareparticularly because of the slowdown of Moore’s law. The main reason of the ineffectiveness ofthe processing speed is the memory wall or Von Neumann bottleneck which is comming from speeddifferences between the processor and the memory. Therefore, a new fast and power-efficient hardwarearchitecture is needed to respond to those huge demands of data processing.In this thesis, we introduce novel high performance architectures for next generation computingusing emerging nanotechnologies such as memristors. We have studied unconventional computingmethods both in the digital and the analog domains. However, the main focus and contribution is inSpiking Neural Network (SNN) or neuromorphic analog computing. In the first part of this dissertation,we review the memristive devices proposed in the literature and study their applicability in a hardwarecrossbar digital architecture. At the end of part I, we review the Neuromorphic and SNN architecture.The second part of the thesis contains the main contribution which is the development of a NeuralNetwork Scalable Spiking Simulator (N2S3) suitable for the hardware implementation of neuromorphiccomputation, the introduction of a novel synapse box which aims at better learning in SNN platforms,a parameter exploration to improve performance of memristor-based SNN, and finally a study of theapplication of deep learning in SNN.On estime que le nombre d’objets connectés à l’Internet atteindra 50 à 100 milliards en 2020. Larecherche s’organise en deux champs principaux pour répondre à ce défi : l’internet des objets etles grandes masses de données. La demande en puissance de calcul augmente plus vite que ledéveloppement de nouvelles architectures matérielles en particulier à cause du ralentissement dela loi de Moore. La raison principale en est est le mur de la mémoire, autrement appelé le gouletd’étranglement de Von Neumann, qui vient des différences de vitesse croissantes entre le processeuret la mémoire. En conséquence, il y a besoin d’une nouvelle architecture matérielle rapide et économeen énergie pour répondre aux besoins énormes de puissance de calcul.Dans cette thèse, nous proposons de nouvelles architectures pour les processeurs de prochainegénération utilisant des nanotechnologies émergentes telles que les memristors. Nous étudions desméthodes de calcul non conventionnelles aussi bien numériques qu’analogiques. Notre contributionprincipale concerne les réseaux de neurones à impulsion (RNI) ou architectures neuromorphiques.Dans la première partie de la thèse, nous passons en revue les memristors existants, étudions leurutilisation dans une architecture numérique à base de crossbars, puis introduisons les architecturesneuromorphiques. La deuxième partie contient la contribution principale : le développement d’unesimulateur d’architectures neuromorphiques (N2S3), l’introduction d’un nouveau type de synapsepour améliorer l’apprentissage, une exploration des paramètres en vue d’améliorer les RNI, et enfinune étude de la faisabilité des réseaux profonds dans les RNI

Calcul non conventionnel avec des nanocomposants memristifs : du calcul numérique auxaccélérateurs neuromorphiques

By 2020, there will be 50 to 100 billion devices connected to the Internet. Two domains of hot researchto address these high demands of data processing are the Internet of Things (IoT) and Big Data. Thedemands of these new applications are increasing faster than the development of new hardwareparticularly because of the slowdown of Moore’s law. The main reason of the ineffectiveness ofthe processing speed is the memory wall or Von Neumann bottleneck which is comming from speeddifferences between the processor and the memory. Therefore, a new fast and power-efficient hardwarearchitecture is needed to respond to those huge demands of data processing.In this thesis, we introduce novel high performance architectures for next generation computingusing emerging nanotechnologies such as memristors. We have studied unconventional computingmethods both in the digital and the analog domains. However, the main focus and contribution is inSpiking Neural Network (SNN) or neuromorphic analog computing. In the first part of this dissertation,we review the memristive devices proposed in the literature and study their applicability in a hardwarecrossbar digital architecture. At the end of part I, we review the Neuromorphic and SNN architecture.The second part of the thesis contains the main contribution which is the development of a NeuralNetwork Scalable Spiking Simulator (N2S3) suitable for the hardware implementation of neuromorphiccomputation, the introduction of a novel synapse box which aims at better learning in SNN platforms,a parameter exploration to improve performance of memristor-based SNN, and finally a study of theapplication of deep learning in SNN.On estime que le nombre d’objets connectés à l’Internet atteindra 50 à 100 milliards en 2020. Larecherche s’organise en deux champs principaux pour répondre à ce défi : l’internet des objets etles grandes masses de données. La demande en puissance de calcul augmente plus vite que ledéveloppement de nouvelles architectures matérielles en particulier à cause du ralentissement dela loi de Moore. La raison principale en est est le mur de la mémoire, autrement appelé le gouletd’étranglement de Von Neumann, qui vient des différences de vitesse croissantes entre le processeuret la mémoire. En conséquence, il y a besoin d’une nouvelle architecture matérielle rapide et économeen énergie pour répondre aux besoins énormes de puissance de calcul.Dans cette thèse, nous proposons de nouvelles architectures pour les processeurs de prochainegénération utilisant des nanotechnologies émergentes telles que les memristors. Nous étudions desméthodes de calcul non conventionnelles aussi bien numériques qu’analogiques. Notre contributionprincipale concerne les réseaux de neurones à impulsion (RNI) ou architectures neuromorphiques.Dans la première partie de la thèse, nous passons en revue les memristors existants, étudions leurutilisation dans une architecture numérique à base de crossbars, puis introduisons les architecturesneuromorphiques. La deuxième partie contient la contribution principale : le développement d’unesimulateur d’architectures neuromorphiques (N2S3), l’introduction d’un nouveau type de synapsepour améliorer l’apprentissage, une exploration des paramètres en vue d’améliorer les RNI, et enfinune étude de la faisabilité des réseaux profonds dans les RNI

Parameter Exploration to Improve Performance of Memristor-Based Neuromorphic Architectures

International audienceThe brain-inspired spiking neural network neuromorphic architecture offers a promising solution for a wide set of cognitive computation tasks at a very low power consumption. Due to the practical feasibility of hardware implementation, we present a memristor-based model of hardware spiking neural networks which we simulate with N2S3 (Neural Network Scalable Spiking Simulator), our open source neuromorphic architecture simulator. Although Spiking neural networks are widely used in the community of computational neuroscience and neuromorphic computation, there is still a need for research on the methods to choose the optimum parameters for better recognition efficiency. With the help of our simulator, we analyze and evaluate the impact of different parameters such as number of neurons, STDP window, neuron threshold, distribution of input spikes and memristor model parameters on the MNIST handwritten digit recognition problem. We show that a careful choice of a few parameters (number of neurons, kind of synapse, STDP window and neuron threshold) can significantly improve the recognition rate on this benchmark (around 15 points of improvement for the number of neurons, a few points for the others) with a variability of 4 to 5 points of recognition rate due to the random initialization of the synaptic weights

Memristor nanodevice for unconventional computing:review and applications

A memristor is a two-terminal nanodevice that its properties attract a wide community of researchers from various domains such as physics, chemistry, electronics, computer and neuroscience.The simple structure for manufacturing, small scalability, nonvolatility and potential of using inlow power platforms are outstanding characteristics of this emerging nanodevice. In this report,we review a brief literature of memristor from mathematic model to the physical realization. Wediscuss different classes of memristors based on the material used for its manufacturing. Thepotential applications of memristor are presented and a wide domain of applications are explainedand classified